11月13日上午 (Morning, Nov 13) |
8:00 - 8:30 | Registration |
8:30 - 9:00 | Invited Speech:Innovating In the New Golden Age of Computer Architecture: Microchip FPGA Business Unit’s RISC-V Case Study
Speaker:Ted Speers (RISC-V基金会,RISC-V Foundation; 微芯科技,Micro-Chip) |
Session 3:
Support and Verification
(Part I)
(9:00 - 10:15)
Chaired by Jianying Peng from 芯来科技 (Nuclei System Technology) | 10. The Importance of Processor Trace in Complex Real-Time Heterogeneous Systems    (Slides)
Hanan Moller and Lisa Yang (UltraSoC Technologies) |
11. Building RISC-V Cloud Computing Ecosystem    (Slides)
Zhipeng Huang (华为,Huawei) |
12. 升级RISC-V的指令级仿真器Spike的缓存模型    (Slides)
Zhenzhen Li and Wei Song (中科院信工所,Institute of Information Engineering, Chinese Academy of Sciences) |
13. A Formal Methodology for Verifying RISC-V Cores    (Slides)
Tom Anderson, Wei Wei Chen and Nicolae Tusinschi (OneSpin Solutions) |
14. EasyDiff: An Effective and Efficient Framework for Processor Verification    (Slides)
余子濠 Zihao Yu (中科院计算所,Institute of Computing Technology, Chinese Academy of Sciences) |
10:15 - 10:35 | Coffee Break (一层大厅) |
Session 4:
Architecture
(10:35 - 12:05)
Chaired by Yubin Xia from
(上海交通大学, Shanghai Jiao Tong University) |
15. Evaluating the Impact of Vector Chaining on RISC-V Vector Extension
Chen Wei and Wei-Chung Hsu (国立台湾大学,National Taiwan University) |
16. 端云相融,普惠创芯
陈志坚 Zhijian Chen and 陈晨 Chen Chen (阿里巴巴平头哥半导体, T-Head semiconductor) |
17. 130nm 高可靠SOI嵌入式RISC-V处理器的研究    (Slides)
Bingtao Qiao, Mo Zhou, Yunlong Zheng, Yi Shan and Yemin Dong
(信息功能材料国家重点实验室,中国科学院上海微系统与信息技术研究所;
材料与光电研究中心,中国科学院大学) (State Key laboratory of functional materials for informatics, SIMIT, CAS ) |
18. Hybrid Architecture Processor Design Based on RISC-V Instruction Set    (Slides)
Xu Wang, Lisi Li, Shuo Zhao (厦门半导体投资,Xiamen Semiconductor Investment Group Co., Ltd.)
and Hu He (清华大学,Tsinghua University) |
19. A High-Performance and Energy-Efficient Accelerator with the RISC-V Core for Optimization in Visual SLAM System    (Slides)
李任伟 Renwei Li, 吴军宁 Junning Wu, 刘檬 Meng Liu, 周沈刚 Shengang Zhou and 陈祖玎 Zuding Chen
(中科院自动化所, Institute of Automation, Chinese Academy of Sciences;
北京中科昊芯科技有限公司, Beijing Haawking Technology Co., Ltd) |
20. RISC-V体系在转发数据面软硬件协同加速的应用探索
熊先奎 Xiankui Xiong, 张景涛 Jingtao Zhang, 张启明 Qiming Zhang and 董德吉 Deji Dong (中兴通讯股份有限公司, ZTE Corporation) |
12:05 - 13:20 | 午餐时间 Lunch Time (大学城内,快乐食间; Happy Hour, University Town) |
11月13日下午 (Afternoon, Nov 13) |
13:20 - 13:40 | Invited Speech:RISC-V生态中知识产权的归属与使用    (Slides)
Speaker:Pascal Jiang (大成律师事务所, Dentons)
|
13:40 - 14:10 | Invited Speech: CHIPS Alliance Project    (Slides)
Speaker:Zvonimir Bandic (CHIPS Alliance; Western Digital Corporation) |
Session 5:
Support and Verification
(Part II)
(14:10 - 15:25)
Chaired by
Fengwei Zhang from
(南方科技大学, Southern University of Science and Technology) |
31. Full Stack Software-Hardware Codesign    (Slides)
Cissy Yuan (新思科技,Synopsys) |
32. Rebuild IC Front End with Chisel: An Example Study of RISC-V Vector Processor    (Slides)
马立伟 Liwei Ma (上海赛昉科技,Sifive China) |
33. 思沃(SERVE):面向RISC-V生态的系统级原型验证服务平台    (Slides)
张科 Ke Zhang, 常轶松 Yisong Chang, 余子濠 Zihao Yu, 唐丹 Dan Tang, 王诲喆 Huizhe Wang, 于磊 Lei Yu, 张旭 Xu Zhang, 赵然 Ran Zhao and 包云岗 Yungang Bao
(中科院计算所,Institute of Computing Technology, Chinese Academy of Sciences)
|
34. RISC-V处理器的可信验证    (Slides)
冯浩 Hao Feng (深圳优矽科技, UC Techip) |
35. Expanding RISC-V Ecosystem with VEGAboard / VEGA-Lite    (Slides)
Jerry Zeng (NXP半导体) |
15:25 - 15:45 | Coffee Break (一层大厅) |
Session 6:
Deep Learning
(15:45 - 16:15)
Chaired by Yanjun Wu from
(中科院软件所, The Institute of Software, Chinese Academy of Sciences) |
38. 针对RISC-V的轻量级深度学习推理框架InferXLite    (Slides)
张先轶 Xianyi Zhang, 向春阳 Chunyang Xiang, 张宾 Bin Zhang and 褚双伟 Shuangwei Chu (澎峰科技, PerfXLab) |
39. 一个面向RISC-V的深度学习推理框架的设计与实现    (Slides)
Pengpeng Hou, Jiageng Yu, Yuxia Miao, Yang Tai, Yanjun Wu and Chen Zhao
(中科院软件所,The Institute of Software, Chinese Academy of Sciences) |
Session 7:
System Software and Compilers
(16:15 - 17:30)
Chaired by Yanjun Wu from
(中科院软件所, The Institute of Software, Chinese Academy of Sciences) | 40. Fedora on RISC-V Status and practice    (Slides)
傅炜 Wei Fu (红帽,Red Hat software (Beijing) Ltd.) |
41. Getting the most out of your professional RISC-V compiler and debugger    (Slides)
Robert DeOliveira (IAR Systems) |
42. 基于软件供应链的应对RISC-V碎片化的操作系统定制平台    (Slides)
Peng Zhou, Guanyu Liang, Jiageng Yu, Jianmin Wang, Yanjun Wu and Chen Zhao
(中科院软件所,Institute of software, Chinese Academy of Sciences) |
43. An Introduction to RISC-V Boot flow: Overview, Blob vs Blobfree standards    (Slides)
Jagan Teki(Amarula Solutions) |
44. RISC-V二进制代码密度分析    (Slides)
刘曜 Yao Liu and 孙海燕 Haiyan Sun (国防科技大学计算机学院,
College of Computer Science and Technology, National University of Defense Technology) |
Panel Session:
17:30 - 18:30 | Topic 1: Venture Capital and Investment for RISC-V in China
Topic 2: RISC-V Applications and Ecosystem
嘉宾(VC): 光速中国、中芯聚源、达泰资金、道易投资;
嘉宾(Industry):阿里平头哥(T-Head semiconductor)、Imagination
Zvonimir Bandic(Western Digital VP and Foundation BoD member)、
Ted Marena(RISC-V Foundation Marketing Committee Chair) |