Introduction

November 12-13, 2019:   China RISC-V Forum, ShenZhen, China

   RISC-V is growing up very fast in China these years, and the open source silicon development ecosystem is getting more and more improved. It shows up at the emerging areas such as IoT, AI, Self-driving, edge computing and makes a lot of innovation and changes from computer architecture ISA to system SW. It is a clear trend that microprocessor design and development based the open source ISA becomes more and ore important in IT industry.
   In the 2019 China RISC-V forum, we want to identify the challenges in building an open and free ecosystem of RISC-V, and pay special attention to the industrial and academic efforts, innovations and projects on RISC-V in China, including but not limited to FPGA and IC based chip design (both high performance and low-power), compiler and system software support, design tool flow, domain specific design and application, and so on.
   We invite practitioners, academicians, and researchers who are passionate about advancing RISC-V ecosystem to join us.
The Forum is open for registration and submission: Register Link       Submission Link

Registration deadline:Nov 5, 2019    Nov 7, 2019 (The program is released.)

Call for Presentation

  The Forum will include a full range of plenary keynotes, academic sessions, and social events. Oral presentation and posters on high-level overview, forward thinking, groundbreaking ideas, and specific technical challenge are all positively encouraged. The speaking lineup and program are selected based on the topic/content submitted and the speaker’s qualifications by the program committee. The topics include but not limit to: ( Download the pdf )

  • RISC-V core design, including Out-Of-Order, Low-power, ….
  • RISC-V System SW, including compiler, debugger, OS, profiler, ...
  • Design tools, Open Source EDA, such as RTL simulator, DFT,…
  • Domain Specific Architecture like AI, IoT, Self-Drive Car, ….
  • Based on RISC-V core SoC design
  • RISC-V application lib standard interface
  • Education on RISC-V

Important Date

Submission: Oct 20,2019 AOE
Notification:

Oct 27,2019 AOE

Nov 2,2019 AOE

AOE (Anywhere on Earth) dates shown above mean the deadlines are at 11:59pm UTC -12:00 of the days.










Organization

Organizers:

RIOS : RISC-V International Open Source Research Laboratory and TBSI : Tsinghua-Berkeley Shenzhen Institute
RISC-V Foundation China Committee
CRVA (China RISC-V Alliance) and ICT (Institute of Computing Technology) at CAS (Chinese Academy of Sciences)


Organizing Committee

General Chair:

Zhangxi Tan
Tsinghua-Berkeley Shenzhen Institute    Adjunct Professor
RISC-V International Open Source Research Laboratory    Deputy Director

Steering Committee Chair:

Jesse Fang
RISC-V Foundation China Committee    Chair
Pre Senior Vice President of Intel，Managing Director of Intel Labs China
Tangram Technologies    CEO/Chairman of Board

Program Committee Chair:

Yungang Bao
China RISC-V Alliance    Secretary-General
Institute of Computing Technology, Chinese Academy of Sciences    Professor
Open Source Chip Academician Studio, Pengcheng Lab    Executie Manager

Local Chair:

Victor Chan
Tsinghua-Berkeley Shenzhen Institute    Vice President


Program Committee
Charlie Su    Andes Technology
Yu Chen    Tsinghua University
Weimin Dai    VeriSilicon
Donglai Dai    Tangram Technologies
Zhenbo Hu    Nuclei System Technology
Jianyi Meng    Pingtou Ge(Brother Pingtou) Semiconductor
Wei Song    Institute of Information Engineering,Chinese Academy of Sciences
Dan Tang    Institute of Computing Technology, Chinese Academy of Sciences
Yanjun Wu    Institute of Software, Chinese Academy of Sciences
Cissy Yuan    RivAi
Yubin Xia    Shanghai Jiao Tong University

Keynotes

We are very honored to have invited the following experts to give us talks:


David Patterson

University of California, Berkeley    Professor
2017 Turning Award Winner

Bio: David Patterson is the Pardee Professor of Computer Science, Emeritus at the University of California at Berkeley, which he joined after graduating from UCLA in 1976.
Dave's research style is to iden tify critical questions for the IT industry and gather inter-disciplinary groups of faculty and graduate students to answer them. The answer is typically embodied in demonstration systems, and these demonstration systems are later mirrored in commercial products. In addition to research impact, these projects train leaders of our field. The best known projects were Reduced Instruction Set Computers (RISC), Redundant Array of Inexpensive Disks (RAID), and Networks of Workstations (NOW), each of which helped lead to billion dollar industries.
A measure of the success of proj ects is the list of awards won by Patterson and as his teammates: the ACM A.M. Turing Award, the C & C Prize, the IEEE von Neumann Medal, the IEEE Johnson Storage Award, the SIGMOD Test of Time award, the ACM-IEEE Eckert-Mauchly Award, and the Katayanagi Prize. He was also elected to both AAAS societies, the National Academy of Engineering, the National Academy of Sciences, the Silicon Valley Engineering Hall of Fame, and to be a Fellow of the Computer History Museum. The full list includes about 40 awards for research, teaching, and service.
In his spare time he coauthored seven books---including two with John Hennessy who is past President of Stanford University and with whom he shared the Turing Award--- Patterson also served as Chair of the Computer Science Division at UC Berkeley, Chair of the Computing Research Association, and President of ACM.

Calista Redmond

RISC-V Foundation    CEO
Pre Vice President of IBM

Bio: Calista Redmond is the CEO of the RISC-V Foundation with a mission to expand and engage RISC-V stakeholders, compel industry adoption, and increase visibility and opportunity for RISC-V within and beyond the Foundation. Prior to the RISC-V Foundation, Calista held a variety of roles at IBM, including Vice President of IBM Z Ecosystem where she led strategic relationships across software vendors, system integrators, business partners, developer communities, and broader engagement across the industry. Focus areas included execution of commercialization strategies, technical and business support for partners, and matchmaker to opportunities across the IBM Z and LinuxOne community. Calista’s background includes building and leading strategic business models within IBM’s Systems Group through open source initiatives including OpenPOWER, OpenDaylight, and Open Mainframe Project. For OpenPOWER, Calista was a leader in drafting the strategy, cultivating the foundation of partners, and nurturing strategic relationships to grow the org from zero to 300+ members. While at IBM, she also drove numerous acquisition and divestiture missions, and several strategic alliances. Prior to IBM, she was an entrepreneur in four successful start-ups in the IT industry. Calista holds degrees from the University of Michigan and Northwestern University.

Ted Speers

RISC-V Foundation    Director
Micro-Chip    Vice President

Bio: Ted Speers is head of product architecture and planning for Microchip’s FPGA BU, where he is responsible for defining its roadmap for low power, secure, reliable FPGAs and SoC FPGAs. He joined Actel (now part of Microchip) in 1987 and held roles in process engineering and product engineering before assuming his current role in 2003. Ted is has served on the board of directors of the RISC-V Foundation since its inception in 2016.  He is a Technical Fellow and co-inventor on 35 U.S. patents. Prior to joining Actel, he worked at LSI Logic. Ted has a Bachelor of Science in chemical engineering from Cornell.

Shijiang Wang

China Center for Information Industry Development IC Industry Research Institute    Director

Bio: 王世江，博士，高级工程师，毕业于中国科学院半导体研究所，现为中国电子信息产业发展研究院集成电路研究所所长，中国半导体行业协会副秘书长，中国光伏行业协会副秘书长。从事电子信息产业、新能源产业、集成电路产业发展规划与技术研发等方面的工作，对集成电路、光伏产业等有深入研究。曾参与国务院关于促进光伏产业健康发展的若干意见、国家集成电路产业发展推进纲要等政策编制工作。在专业刊物和会议上发表文章30篇以上，其中SCI收录文章14篇，出版专著一部等。

Alex Wang

Powerchip Technology    President
RISC-V Taiwan Alliance    Chairman

Bio: 王其国博士现任(台湾)力晶科技公司总经理，在半导体产业有35年技术研发、事业管理经验。在2005年参加力晶前担任(台湾)华邦电子公司记忆产品事业群总经理。曾在(美国硅谷)创业Programmable Microelectronics 公司任CEO，并曾服务于Fairchild, Intel和Samsung 公司。王其国毕业于国立台湾大学，并获美国香槟城伊利诺大学硕士及博士学位，指导教授为CMOS发明人萨支唐 (C.T. Sah)教授。

Pascal Jiang

Dentons    Partner

Bio: 江苗律师系上海大成合伙人，其业务领域包括科技、媒体和电信行业、文化娱乐业及对外投资。江律师擅长在高度监管的行业中，为中方或外方的市场准入设计合适的投资和合作结构，完善各方的合作安排。江律师在知识产权保护方面有十余年的法律服务经验，其服务客户的行业涵盖互联网、软件、零售（线上和线下）、移动支付、无人驾驶、云服务、大数据分析等。江律师对知识产权许可和保护有丰富的经验和独到的见解。

Zvonimir Bandic

CHIPS Alliance
Western Digital Corporation

Bio: Zvonimir Z. Bandić is the Research Staff Member and Senior Director of Next Generation Platform Technologies Department in a Western Digital Corporation in San Jose, California. He received his BS in electrical engineering in 1994 from the University of Belgrade, Yugoslavia, and his MS (1995) and PhD (1999) in applied physics from Caltech, Pasadena, in the field of novel electronic devices based on wide bandgap semiconductors. He is currently focusing on emerging Non-Volatile Memories (PCM, ReRAM, MRAM) applications for data center distributed computing, including RISC-V based CPU technologies , in-memory compute, RDMA networking, and machine learning hardware acceleration. He has been awarded over 50 patents in the fields of solid state electronics, solid state disk controller technology, security architecture and storage systems and has published over 50 peer-reviewed papers. Zvonimir is Chairman of CHIPS Alliance, Chair of OpenCAPI org, and Board of Directors member of RISC-V standards organization.

Call for Presentations

  The Forum will include a full range of plenary keynotes, academic sessions, and social events. Oral presentation and posters on high-level overview, forward thinking, groundbreaking ideas, and specific technical challenge are all positively encouraged. The speaking lineup and program are selected based on the topic/content submitted and the speaker’s qualifications by the program committee. The topics include but not limit to: ( Download the pdf )

  • RISC-V core design, including Out-Of-Order, Low-power, ….
  • RISC-V System SW, including compiler, debugger, OS, profiler, ...
  • Design tools, Open Source EDA, such as RTL simulator, DFT,…
  • Domain Specific Architecture like AI, IoT, Self-Drive Car, ….
  • Based on RISC-V core SoC design
  • RISC-V application lib standard interface
  • Education on RISC-V

Important Date

Submission: Oct 20,2019 AOE
Notification:

Oct 27,2019 AOE

Nov 2,2019 AOE

AOE (Anywhere on Earth) dates shown above mean the deadlines are at 11:59pm UTC -12:00 of the days.

Welcome to CRVF-2019

Guidelines

  • Papers must be submitted in PDF format and should contain a maximum of 2 pages of single-spaced two-column text, excluding references and appendices.
  • No specific template, but ACM template is recommended.
  • Both unpublished and published papers/technical reports.
  • Reviewing will be OPR(Open Peer Review). The author list and contact information(email address) should be included in the paper.

Submissions

Please submit your paper here： Submissions

Any questions on CFP and submission, please contact: xiebiwei(at)ict.ac.cn .

论坛议程 (Program)

报告和Poster标题前的序号，表明了它们在Lighning Session的演讲顺序，以及在Poster Session的编号

The number in front of the talk and poster indicates the sequence of lightning talk. It is also the ID in poster session.

点击此处，下载所有Slides (Download All Slides in an All-in-One Zip File)

11月12日上午 (Morning, Nov 12)

8:00 - 8:30
 Registration
8:30 - 8:45
 Opening Remark
8:45 - 9:40
 Keynote Speech：RISC-V Architecture and the RISC-V International Open Source Laboratory at the Tsinghua-Berkeley Shenzhen Institute    (Slides)
Spaker： David Patterson (加州大学伯克利分校，University of California, Berkeley)
9:40 - 10:00
 Coffee Break (一层大厅)
10:00 - 10:30
 Invited Speech：中国开源硬件的机遇与挑战
王世江 Shijiang Wang (工信部赛迪研究院集成电路研究所, China Center for Information Industry Development IC Industry Research Institute)
10:30 - 11:00
 Invited Speech ：Growing Momentum and Opportunity of RISC-V Open Architecture    (Slides)
Speaker：Calista Redmond (RISC-V基金会，RISC-V Foundation)
Lightning Session
(11:00 - 12:00)

Chaired by Zhijian Chen
from 平头哥半导体 ( T-Head semiconductor)
 每个Talk 和 Poster 做一分钟快速报告, Each talk/poster has 1 minute to show her/his work
12:00 - 13:30
 午餐时间 Lunch Time (大学城内，快乐食间; Happy Hour, University Town)

11月12日下午 (Afternoon, Nov 12)

13:30 - 14:00
 Invited Speech： RISC-V Taiwan Alliance (RVTA) Update    (Slides)
Speaker：王其国 Alex Wang (力晶科技，Powerchip Technology; 台湾RISC-V联盟，RISC-V Taiwan Alliance)
Session 1:Security
(14:00 - 15:15)

Chaired by Cissy Yuan
from 睿思芯科 (RivAi)
 01. A high-performance secure RISC-V core for embedded applications
戴东来 Donglai Dai (致象尔微电子，Tangram Technologies)
02. SecLabel: Enhancing RISC-V Platform Security with Labelled Architecture    (Slides)
Zhenyu Ning(韦恩州立大学，南方科技大学，Wayne State University and Southern University of Science and Technology), Yinqian Zhang(俄亥俄州立大学，The Ohio State University) and Fengwei Zhang(南方科技大学，Southern University of Science and Technology)
03. Penglai-Enclave: Secure and Efficient RISC-V Enclave    (Slides)
杜东 Dong Du, 路旭 Xu Lu, 冯二虎 Erhu Feng, 杨璧丞 Bicheng Yang, 夏虞斌 Yubin Xia and 陈海波 Haibo Chen (上海交通大学，Shanghai Jiao Tong University)
04. An Enclave-based TEE for SE-in-SoC in RISC-V Industry
崔晓夏 Xiaoxia Cui (平头哥半导体，T-Head semiconductor)
05. 高可靠性高安全性RISC-V处理器设计和实现    (Slides)
胡振波 Bob Hu, 徐来 Tony Xu and 彭剑英 Jianying Peng (芯来科技，Nuclei System Technology)
Session 2:
Deep Learning
(15:15 - 15:45)

Chaired by Cissy Yuan
from 睿思芯科 (RivAi)
 07. Shaping Student’s System Basics by Building a RISC-V Computer System with ProjectN    (Slides)
余子濠 Zihao Yu (中科院计算所，Institute of Computing Technology, Chinese Academy of Sciences) and 袁春风 Chunfeng Yuan (南京大学，Nanjing University)
08. 基于RISC-V的操作系统教学尝试    (Slides)
宫晓利 Xiaoli Gong(南开大学，Nankai University), 李先铎 Xianduo Li(中国矿业大学，China University of Mining and Technology), 方睿丽 Ruili Fang(南开大学，Nankai University), 张蔚 Wei Zhang and 向勇 Yong Xiang(清华大学，Tsinghua University)
15:45 - 16:45
 Poster Session & Coffee Break (一层大厅)
(Poster列表请见最后的附表, Please find the Poster List at the end of the program)
16:45 - 18:00
 乘坐大巴赴五洲宾馆参加 RIOS 揭牌仪式和 banquet (Go to Wuzhou Guest House by shuttle bus)
18:00 - 19:00
 RIOS揭牌仪式 Opening Ceremony of RIOS (五洲宾馆, Wuzhou Guest House)
19:00 - 21:00
 晚宴 Banquet (五洲宾馆, Wuzhou Guest House) and Poster 展示
21:00 - 21:30
 晚宴后乘坐大巴返回会场附近酒店，视现场人数可能会分多个班次，具体班次待定。
(Go back by shuttle bus)
注：返程大巴将停靠：会场，以及论坛推荐酒店（列表请见网站）


11月13日上午 (Morning, Nov 13)

8:00 - 8:30
 Registration
8:30 - 9:00
 Invited Speech：Innovating In the New Golden Age of Computer Architecture: Microchip FPGA Business Unit’s RISC-V Case Study
Speaker：Ted Speers (RISC-V基金会，RISC-V Foundation; 微芯科技，Micro-Chip)
Session 3:
Support and Verification
(Part I)
(9:00 - 10:15)

Chaired by Jianying Peng
from 芯来科技 (Nuclei System Technology)
 10. The Importance of Processor Trace in Complex Real-Time Heterogeneous Systems    (Slides)
Hanan Moller and Lisa Yang (UltraSoC Technologies)
11. Building RISC-V Cloud Computing Ecosystem    (Slides)
Zhipeng Huang (华为，Huawei)
12. 升级RISC-V的指令级仿真器Spike的缓存模型    (Slides)
Zhenzhen Li and Wei Song
(中科院信工所，Institute of Information Engineering, Chinese Academy of Sciences)
13. A Formal Methodology for Verifying RISC-V Cores    (Slides)
Tom Anderson, Wei Wei Chen and Nicolae Tusinschi (OneSpin Solutions)
14. EasyDiff: An Effective and Efficient Framework for Processor Verification    (Slides)
余子濠 Zihao Yu (中科院计算所，Institute of Computing Technology, Chinese Academy of Sciences)
10:15 - 10:35
 Coffee Break (一层大厅)
Session 4:
Architecture
(10:35 - 12:05)

Chaired by Yubin Xia from
(上海交通大学, Shanghai Jiao Tong University)
15. Evaluating the Impact of Vector Chaining on RISC-V Vector Extension
Chen Wei and Wei-Chung Hsu (国立台湾大学，National Taiwan University)            
16. 端云相融，普惠创芯
陈志坚 Zhijian Chen and 陈晨 Chen Chen (阿里巴巴平头哥半导体, T-Head semiconductor)
17. 130nm 高可靠SOI嵌入式RISC-V处理器的研究    (Slides)
Bingtao Qiao, Mo Zhou, Yunlong Zheng, Yi Shan and Yemin Dong
(信息功能材料国家重点实验室，中国科学院上海微系统与信息技术研究所； 材料与光电研究中心，中国科学院大学) (State Key laboratory of functional materials for informatics, SIMIT, CAS )
18. Hybrid Architecture Processor Design Based on RISC-V Instruction Set    (Slides)
Xu Wang, Lisi Li, Shuo Zhao (厦门半导体投资，Xiamen Semiconductor Investment Group Co., Ltd.)
and Hu He (清华大学，Tsinghua University)
19. A High-Performance and Energy-Efficient Accelerator with the RISC-V Core for Optimization in Visual SLAM System    (Slides)
李任伟 Renwei Li, 吴军宁 Junning Wu, 刘檬 Meng Liu, 周沈刚 Shengang Zhou and 陈祖玎 Zuding Chen (中科院自动化所, Institute of Automation, Chinese Academy of Sciences； 北京中科昊芯科技有限公司, Beijing Haawking Technology Co., Ltd)
20. RISC-V体系在转发数据面软硬件协同加速的应用探索
熊先奎 Xiankui Xiong, 张景涛 Jingtao Zhang, 张启明 Qiming Zhang and 董德吉 Deji Dong (中兴通讯股份有限公司, ZTE Corporation)
12:05 - 13:20
 午餐时间 Lunch Time (大学城内，快乐食间; Happy Hour, University Town)

11月13日下午 (Afternoon, Nov 13)

13:20 - 13:40
 Invited Speech：RISC-V生态中知识产权的归属与使用    (Slides)
Speaker：Pascal Jiang (大成律师事务所, Dentons)
13:40 - 14:10
Invited Speech：CHIPS Alliance Project    (Slides)
Speaker：Zvonimir Bandic (CHIPS Alliance; Western Digital Corporation)
Session 5:
Support and Verification
（Part II）
(14:10 - 15:25)

Chaired by
Fengwei Zhang from
(南方科技大学, Southern University of Science and Technology)
 31. Full Stack Software-Hardware Codesign    (Slides)
Cissy Yuan (新思科技，Synopsys)
32. Rebuild IC Front End with Chisel: An Example Study of RISC-V Vector Processor    (Slides)
马立伟 Liwei Ma (上海赛昉科技，Sifive China)
33. 思沃(SERVE)：面向RISC-V生态的系统级原型验证服务平台    (Slides)
张科 Ke Zhang, 常轶松 Yisong Chang, 余子濠 Zihao Yu, 唐丹 Dan Tang, 王诲喆 Huizhe Wang, 于磊 Lei Yu, 张旭 Xu Zhang, 赵然 Ran Zhao and 包云岗 Yungang Bao
(中科院计算所，Institute of Computing Technology, Chinese Academy of Sciences)
34. RISC-V处理器的可信验证    (Slides)
冯浩 Hao Feng (深圳优矽科技, UC Techip)
35. Expanding RISC-V Ecosystem with VEGAboard / VEGA-Lite    (Slides)
Jerry Zeng (NXP半导体)
15:25 - 15:45
 Coffee Break (一层大厅)
Session 6:
Deep Learning
(15:45 - 16:15)

Chaired by Yanjun Wu from
(中科院软件所, The Institute of Software, Chinese Academy of Sciences)
38. 针对RISC-V的轻量级深度学习推理框架InferXLite    (Slides)
张先轶 Xianyi Zhang, 向春阳 Chunyang Xiang, 张宾 Bin Zhang and 褚双伟 Shuangwei Chu (澎峰科技, PerfXLab)
39. 一个面向RISC-V的深度学习推理框架的设计与实现    (Slides)
Pengpeng Hou, Jiageng Yu, Yuxia Miao, Yang Tai, Yanjun Wu and Chen Zhao
(中科院软件所，The Institute of Software, Chinese Academy of Sciences)
Session 7:
System Software and Compilers
(16:15 - 17:30)

Chaired by Yanjun Wu from
(中科院软件所, The Institute of Software, Chinese Academy of Sciences)
 40. Fedora on RISC-V Status and practice    (Slides)
傅炜 Wei Fu (红帽，Red Hat software (Beijing) Ltd.)
41. Getting the most out of your professional RISC-V compiler and debugger    (Slides)
Robert DeOliveira (IAR Systems)
42. 基于软件供应链的应对RISC-V碎片化的操作系统定制平台    (Slides)
Peng Zhou, Guanyu Liang, Jiageng Yu, Jianmin Wang, Yanjun Wu and Chen Zhao
(中科院软件所，Institute of software, Chinese Academy of Sciences)
43. An Introduction to RISC-V Boot flow: Overview, Blob vs Blobfree standards    (Slides)
Jagan Teki（Amarula Solutions）
44. RISC-V二进制代码密度分析    (Slides)
刘曜 Yao Liu and 孙海燕 Haiyan Sun (国防科技大学计算机学院， College of Computer Science and Technology, National University of Defense Technology)
Panel Session:

17:30 - 18:30
 Topic 1: Venture Capital and Investment for RISC-V in China
Topic 2: RISC-V Applications and Ecosystem

嘉宾（VC）: 光速中国、中芯聚源、达泰资金、道易投资；
嘉宾（Industry）：阿里平头哥(T-Head semiconductor)、Imagination
Zvonimir Bandic（Western Digital VP and Foundation BoD member）、
Ted Marena（RISC-V Foundation Marketing Committee Chair）


Poster List:
06. SCRx family of the RISC-V compatible processor IP by Syntacore
Pavel Khabarov and Alexander Redkin（Syntacore）
09. 一种面向RISC-V的编译原理教学方案探索    (Slides)
Hongbin Zhang, Liutong Han, Mingjie Xing, Yanjun Wu and Chen Zhao
(中科院软件所，Institute of software, Chinese Academy of Sciences)
21. 基于蜂鸟E203处理器的导航SoC设计
Shuang Qin, Jian Li, Ying Yang and Jie Chen
(中科院微电子所，Institute of Microelectronics of the Chinese Academy of Sciences)
22. 基于RISC-V指令集的AIoT芯片计算架构设计
曹英杰 Yingjie Cao, 于欣 Xin Yu and 蒋寿美 Shoumei Jiang (时擎科技, TimesIntelli)
23. Domain-Specific Processor Design Featuring the RISC-V ISA    (Slides)
Markus Willems and Baolu Zhai（新思科技，Synopsys）
24. 可参数化的乱序与多发射RISCV处理器设计方案探索
Xinbing Li （ECNU）
25. 一种RISC-V指令集余数指令的实现方法
刘权胜 Quansheng Liu（中科睿芯，SmartCore） and 孙浩 Hao Sun（华米科技，Huami）
26. Study of Different Cache Line Replacement Algorithms on RISC-V
Xiaolin Li, Qinfen Hao, Kunming Zhang, Shengjian Lu and Chenglong Zhang
(中科院计算所，Institute of Computing Technology, Chinese Academy of Sciences)
27. 基于资源复用的RISC-V处理器设计方法
位国清 Guoqing Wei, 胡珍 Zhen Hu, 贠晨阳 Chenyang Yun and 董杰 Jie Dong（中兴微电子，Sanechips Technology）
28. 基于RISC-V构建端云融合及BMC专用SoC研究
李仁刚 Rengang Li, 李拓 Tuo Li(浪潮电子信息产业股份有限公司，Inspur Electronic Information Industry Co.,Ltd), 王成齐 Chengqi Wang(北京导航中心工程部), 邹晓峰 Xiaofeng Zou, 林宁亚 Ningya Lin and 刘同强 Tongqiang Liu(浪潮电子信息产业股份有限公司，Inspur Electronic Information Industry Co.,Ltd)
29. RISC-V处理器在产业中的应用情况梳理
董杰 Jie Dong, 寇楠 Nan Kou, 位国清 Guoqing Wei and 贠晨阳 Chenyang Yun（中兴微电子，Sanechips Technology）
30. RISC-V encryption virtualisation
Mahdi Boutchacha（阿尔及利亚，Algeria）
36. A Framework for RISC-V Processor Verification
Xiguang Wu, Fan Zhang, Qiang Li, Rui Chen and Lei Guo (鹏城实验室，Peng Cheng Laboratory)
37. RISC-V 图形化编程设计实践    (Slides)
Xiao Zheng Lai, Ruo Hui Chen and Guo Yi Mo（华南理工大学 计算机科学与工程学院，Computer Science and Engineering College, South China University of Technology）
45. 基于RTL代码替换的Chisel编写的DLA的验证
李之南 Zhinan Li，卢向南 Xiangnan Lu，陈逸杰 Yijie Chen，徐频捷 Pinjie Xu and 赵地 Di Zhao (中科院计算所，Institute of Computing Technology, Chinese Academy of Sciences)
46. Design and implementation of a LLVM RISC-V backend
Shan Hai and Ming Hai（北京译芯科技, Beijing Compilab Ltd.）

Registration

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Conference Venue

The conference will be held in Lecture Hall, 3F, CII Building, Tsinghua Shenzhen International Graduate School, University Town, Nanshan District, Shenzhen·China
Address:No. 2279 Lishui Road, Nanshan District, Shenzhen City, Guangdong Province

Location in the map:

Hotel Information

1.Xi Li Lake Holiday Resort ★★★☆☆

1.1 Price: 300-600 RMB
1.2 Address: No. 4001, Xi Li Lake Road, Nanshan District, Shenzhen
1.3 Phone:（0755）26511888

2.Jinbaihe Hotel ★★★★☆

2.1 Price: 420-500 RMB
2.2 Address: No. 4038, Xi Li Lake Road, Nanshan District, Shenzhen
2.3 Phone:（0755）26626666

3.Vienna Hotel (Shenzhen University City) ★★★★☆

3.1 Price: 390-610 RMB
3.2 Address: No. 385, Ping Shang First Road, Ping Shan Cun, Xi Li Town, Nanshan District, Shenzhen
3.3 Phone: (0755)26723888

4.Lavande Hotel (Shezhen University Town Metro Station)

4.1 Price: 420-520 RMB
4.2 Address: No. 1 Building, Da Yuan Industrial Area, Ping Shan First Road, Nanshan District, Shenzhen
4.3 Phone: (0755)26919789

5.Sheraton Shenzhen Nanshan ★★★★★

5.1 Price: 1200-3200
5.2 Address: No. 4088, Liu Xian Road, Nanshan District Shenzhen
5.3 Phone: (0755)22669999

Location in the map: